ECE260: Introduction to Digital Design
Executive Summary
This course explores the foundation of digital circuit design, starting from Boolean algebra, through combinational and sequential logic, to finite state machines and basic central processing units (CPUs) under von Neumann architecture. The associated laboratory segment introduces modern digital design techniques, e.g., Verilog hardware description language (HDL) and field-programmable gate array (FPGA), to model, implement, and test the aforementioned digital circuits. Pre: 160 or 110 or ICS 111 or consent.
Logistics
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CRN
ECE260 001 ECE260 002 86937 86938 -
Personnel
Role / Personnel Assigned Session Office Hours / Notes Lecturer: Yao Zheng N/A see here TA: Ethan Ibanez Session 1 (T 9:00am - 11:45am) TBD TA: Ethan Ibanez Session 2 (T 13:30pm - 16:15pm) TBD -
Classroom
Time Location Textbook/HW HW/Exam Effort MWF 9:30 am-10:20pm Bilger Hall 335 EE260: Introduction to Digital Design Individual -
Laboratory
Session Time Location Report Effort 01 T 9:00am - 11:45am Holmes Hall 451 Group 02 T 13:30pm - 16:15pm Holmes Hall 451 Group
Grading
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Breakdown1
Participation Challenge Labs Midterms (2) Final 5% 20% 25% 20% 30% -
Curves
Linear Bell participation, challenge, labs Midterms, Final -
Cutoffs
A- B- C- 70% 50% 30% -
Proscribed Conduct: Copying or otherwise cheating on homework, lab reports, or exam will result in a failing grade for the course. More details can be found at student conduct code policies, III.C.
Schedule
Lecture
| TIME | TOPICS | READING/HW/EXAM | DEADLINE |
|---|---|---|---|
| Week 1 (1/13, 1/15) | Course Logistic and Introduction | Read/HW 01 | 1/18, 11:59PM |
| Week 2 (1/20, 1/22) | Number Systems | Read/HW 02 | 1/25, 11:59PM |
| Week 3 (1/26, 1/28, 1/30) | Combinational Logic: Switches, Transistors, Logic Gates | Read/HW 03 | 2/1, 11:59PM |
| Week 4 (2/2, 2/4, 2/6) | Combinational Logic: Boolean Algebra | Read/HW 04 | 2/8, 11:59PM |
| Week 5 (2/9, 2/11, 2/13) | Combinational Logic: Design Process, More Gates | Read/HW 05 | 2/15, 11:59PM |
| Week 6 (2/16, 2/18, 2/20) | Encoder, Priority Encoder, Decoder | Read/HW 06 | 2/22, 11:59PM |
| Week 7 (2/23, 2/25, 2/27) | Arithmetic Logic Unit | – | – |
| Weekend 7 (2/27, 2/28, 2/29) | Midterm I: Take Home | Submission link, Solution | 2/29, 06:00PM |
| Week 8 (3/2, 3/4, 3/6) | Sequential Logic: Clock, Latches, and Flip-Flops | Read/HW 07 | 3/8, 11:59PM |
| Week 9 (3/9, 3/11, 3/13) | Sequential Logic: Finite State Machines | Read/HW 08 | 3/15, 11:59PM |
| Week 10 (3/16-3/20) | SPRING RECESS | – | – |
| Week 11 (3/23, 3/25, 3/27) | Sequential Logic: Registers, Counters, Shifters, Arithmetic | Read/HW 09 | 3/29, 11:59PM |
| Week 12 (3/30, 4/1) | Sequential Datapath and Simple Processor Architecture | – | |
| Weekend 12 (4/3, 4/4, 4/5) | Midterm II: Take Home | Submission link, Solution | 4/5, 06:00PM |
| Week 13 (4/6, 4/8, 4/10) | Register-Transfer Level Design | Read/HW 11 | 4/12, 11:59PM |
| Week 14 (4/13, 4/15, 4/17) | Register Memory Components and FIFO | Read/HW 12 | 4/19, 11:59PM |
| Week 15 (4/20, 4/22, 4/24) | Optimizations and Tradeoffs | Read/HW 13 | 4/26, 11:59PM |
| Week 16 (4/27, 4/29, 5/1) | Physical Implementation on ICs | Read/HW 14 | 5/3, 11:59PM |
| Week 17 (5/4, 5/6) | Programmable Processors | Read/HW 15 | 5/10, 11:59PM |
| Study Period (5/7, 5/8) | Review, Practice Final | – | – |
| Finals Week (5/11-5/15) | Final Exam - TBD | – | TBD |
Laboratory
| TIME | Materials | Virtual | DEADLINE |
|---|---|---|---|
| Week 1 (1/13) | – | — | — |
| Week 2 (1/20) | Vivado Tutorial | Vlab 00 | 1/25, 11:59PM |
| Week 3 (1/27) | Modeling Concepts | Vlab 01 | 2/1, 11:59PM |
| Week 4 (2/3) | Numbering Systems | Vlab 02 | 2/8, 11:59PM |
| Week 5 (2/10) | Multi-Output Circuits | Vlab 03 | 2/15, 11:59PM |
| Week 6 (2/17) | Tasks Functions, and Testbench | Vlab 04 | 2/22, 11:59PM |
| Week 7 (2/24) | – | – | – |
| Week 8 (3/3) | Modeling Latches and Flip-Flops | Vlab 05 | 3/8, 11:59PM |
| Week 9 (3/10) | Finite State Machines | Vlab 06 | 3/15, 11:59PM |
| Week 10 (3/17) | SPRING RECESS | – | – |
| Week 11 (3/24) | – | – | – |
| Week 12 (3/31) | Modeling Registers and Counters | Vlab 07 | 4/5, 11:59PM |
| Week 13 (4/7) | Architectural Wizard and IP Catalog | Vlab 08 | 4/12, 11:59PM |
| Week 14 (4/14) | Behavioral Modeling and Timing Constraints | Vlab 09 | 4/19, 11:59PM |
| Week 15 (4/21) | Sequential System Design using ASM Charts | Vlab 10 | 5/3, 11:59PM |
| Week 16 (4/28) | – | – | – |
| Week 17 (5/5) | – | – | – |
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The grading breakdown is subject to change at the discretion of the instructor and in accordance with the University grading system and policies. ↩︎