ECE260: Introduction to Digital Design
Executive Summary
This course explores the foundation of digital circuit design, starting from Boolean algebra, through combinational and sequential logic, to finite state machines and basic central processing units (CPUs) under von Neumann architecture. The associated laboratory segment introduces modern digital design techniques, e.g., Verilog hardware description language (HDL) and field-programmable gate array (FPGA), to model, implement, and test the aforementioned digital circuits. Pre: 160 or 110 or ICS 111 or consent.
Logistics
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CRN
ECE260 001 ECE260 002 88066 88067 -
Personnel
Lecturer: Yao Zheng Office Hours: see here TA: Kamea McMillan Zilberman Session 1, Office Hours: HH451, F 11:00am - 12:00pm TA: Chansen Tano Session 2, Office Hours: HH451, T 04:30pm - 05:30pm Grader: Nathaniel Gideon Castro NA -
Classroom
Time Location Textbook/HW HW/Exam Effort MWF 9:30am-10:20am Miller Hall 2 EE260: Introduction to Digital Design Individual -
Laboratory
Session Time Location Report Effort 01 T 9:00am-11:45am Holmes Hall 451 Group 02 T 1:30pm-4:15pm Holmes Hall 451 Group
Grading
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Breakdown
Participation Challenge Labs Midterms (2) Final 5% 20% 25% 30% 20% -
Curves
Linear Bell participation, challenge, labs Midterms, Final -
Cutoffs
A- B- C- 70% 50% 30% -
Proscribed Conduct: Copying or otherwise cheating on homework, lab reports, or exam will result in a failing grade for the course. More details can be found at student conduct code policies, III.C.
Schedule
Lecture
| TIME | TOPICS | READING/HW/EXAM | DEADLINE |
|---|---|---|---|
| Week 1 (1/13, 1/15, 1/17) | Course Logistic and Introduction | Read/HW 01 | 1/19, 11:59PM |
| Week 2 (1/22 1/24) | Number Systems | Read/HW 02 | 1/26, 11:59PM |
| Week 3 (1/27, 1/29, 1/31) | Combinational Logic: Switches, Transistors, Logic Gates | Read/HW 03 | 2/2, 11:59PM |
| Week 4 (2/3, 2/5, 2/7) | Combinational Logic: Boolean Algebra | Read/HW 04 | 2/9, 11:59PM |
| Week 5 (2/10, 2/12, 2/14) | Combinational Logic: Design Process, More Gates | Read/HW 05 | 2/18, 11:59PM |
| Week 6 (2/19) | Practice Midterm I | – | – |
| Week 6 (2/21) | Midterm I: 9:30AM - 10:20AM | – | – |
| Week 7 (2/24, 2/26, 2/28) | Sequential Logic: Clock, Latches, and Flip-Flops | Read/HW 07 | 3/2, 11:59PM |
| Week 8 (3/3, 3/5, 3/7) | Sequential Logic: Finite State Machines | Read/HW 08 | 3/9, 11:59PM |
| Week 9 (3/10, 3/12, 3/14) | Sequential Logic: Registers, Counters, Shifters, and Arithmetic | Read/HW 09 | 3/16, 11:59PM |
| Spring Recess (3/17 - 3/21) | – | – | – |
| Week 10 (3/24) | Practice Midterm II | – | – |
| Week 10 (3/28) | Midterm II: 9:30AM - 10:20AM | – | – |
| Week 11 (3/31, 4/2, 4/4) | Register-Transfer Level Design | Read/HW 11 | 4/6, 11:59PM |
| Week 12 (4/7, 4/9, 4/11) | Register Memory Components and FIFO | Read/HW 12 | 4/13, 11:59PM |
| Week 13 (4/14, 4/16) | Optimizations and Tradeoffs | Read/HW 13 | 4/20, 11:59PM |
| Week 14 (4/21, 4/23, 4/25) | Physical Implementation on ICs | Read/HW 14 | 4/27, 11:59PM |
| Week 15 (4/28, 4/30, 5/2) | Programmable Processors | Read/HW 15 | 5/4, 11:59PM |
| Week 16 (5/5, 5/7) | Review, Practice Final | – | – |
| Week 17 (5/16) | Final: 9:45AM - 11:45AM | – | 5/16, 11:45AM |
Laboratory
| TIME | Materials | Virtual | DEADLINE |
|---|---|---|---|
| Week 1 (1/14) | – | — | — |
| Week 2 (1/21) | Vivado Tutorial | Vlab 00 | |
| Week 3 (1/28) | Modeling Concepts | Vlab 01 | |
| Week 4 (2/4) | Numbering Systems | Vlab 02 | |
| Week 5 (2/11) | Multi-Output Circuits | Vlab 03 | |
| Week 6 (2/18) | – | – | – |
| Week 7 (2/25) | Tasks Functions, and Testbench | Vlab 04 | 3/2, 11:59PM |
| Week 8 (3/4) | Modeling Latches and Flip-Flops | Vlab 05 | 3/9, 11:59PM |
| Week 9 (3/11) | Finite State Machines | Vlab 06 | 3/16, 11:59PM |
| Spring Recess (3/18) | – | – | – |
| Week 10 (3/25) | – | – | – |
| Week 11 (4/1) | Modeling Registers and Counters | Vlab 07 | 4/6, 11:59PM |
| Week 12 (4/8) | Architectural Wizard and IP Catalog | Vlab 08 | 4/13, 11:59PM |
| Week 13 (4/15) | Behavioral Modeling and Timing Constraints | Vlab 09 | 4/20, 11:59PM |
| Week 14 (4/22) | Sequential System Design using ASM Charts | Vlab 10 | 4/27, 11:59PM |
| Week 15 (4/29) | – | – | |
| Week 16 (5/6) | – | – | – |
| Week 17 (5/13) | – | – | – |