TTL Circuits

• half adder
• full adder
• n-bit adder
• carry-save adder
• 2's complement adder-subtractor

Binary addition, Half Adder

• sum of two bits, a and b, has three possible results:
• a = 0, b = 0, sum = 00
• a = 0, b = 1, sum = 01
• a = 1, b = 0, sum = 01
• a = 1, b = 1, sum = 10
• result bit is a xor b
• carry bit is a and b
• circuit with two inputs, a and b, and two outputs, sum and carry, is a half adder
• what about carry in from the previous bit?

Full Adder

• sum of three bits, a, b, and carry (c):

  a	b	c	sum
  0	0	0	00
  0	0	1	01
  0	1	0	01
  0	1	1	10
  1	0	0	01
  1	0	1	10
  1	1	0	10
  1	1	1	11

• first (less significant) output is result
• second (more significant) output is carry out
• in-class exercise (5 minutes, alone): use two half adders and an OR gate to build this

Full Adder from Half Adders

• sum output of first half adder goes into second half adder
• Carry-in forms other input of second half adder
• sum is the parity of the 3 inputs, so is the sum output of the second half adder: (A XOR B) XOR C
• Carry-out should be ABC + (NOT A)BC + A(NOT B)C + A B (NOT C) = AB + BC + AC
• ORing the two carry output from the half adders computes C . (A XOR B) + AB = C (NOT A) B + C A (NOT B) + AB = (NOT A) B C + A (NOT B) C + AB
• but, AB = ABC + AB (NOT C), so the above rewrites to (NOT A) B C + A (NOT B) C + AB (NOT C) + ABC, which is exactly the desired formula

Multi-bit Adder

• carry out of less significant full adder can be connected to carry in of next full adder to give adder for any size words
• time for carry propagation on addition of size n is proportional to n
• solution ( carry save adder) with log(n) time:
  • carry is generated when we have two "1" inputs (AND is high)
  • carry is propagated when we have at least one "1" input (OR is high)
  • these can be computed on a bit-wise basis
  • carry-in for bit i is high if: generated by bit i-1, or propagated by bit i-1 and generated to the left of bit i-1
  • these carries are computed in time O(log n) by a tree of circuits, then XORed with the input bits to give the sums

Two's complement addition and subtraction

• sign-magnitude: MSB is sign, remainder is the same
• 1's complement: inversion, (not(A))
• 2's complement: A' = (-A) = (not(A)) + 1

2's Complement Adder-Subtractor

• n-bit full adder
• one of the inputs (traditionally, B), goes through an n-bit controlled inverter
• the control line also goes into the carry-in of the adder, so that:
  • when the control line is low, B is unchanged, and the output is A+B+0 (arithmetic addition), since the carry in is zero
  • when the control line is high, B becomes (not(B)) , and the output is A+(NOT B)+1 = A + (- B) = A - B