TTL Circuits

Debouncer circuit

when a switch connects two electrical conductors, there is often some mechanical "bounce"
bounce produces on-off-on-off behavior that is bad for counting, clocking, etc.
debouncer circuit gives a clean on/off signal, using a SPDT (single pole, double throw) switch
when switch moves from high to low contact, output remains constant until low contact is made
after that, low output remains constant until switch contacts the high contact again
in-class exercise: verify that the debouncer works as advertised. When the switch is high, is output A high or low?

in-class exercise: draw/design a multiplexer with:
- 8 inputs, D0-D7
- 3 control lines, A, B, C
- one output Y, which reflects the value of the input corresponding to the numerical value of the control lines (e.g. A = 1, B = 0, C = 0 means 100 = 4, so Y should equal D4).
- hint: think "sum of products"
using multiplexers to implement arbitrary functions

sum of two bits, a and b, has three possible results:
a = 0, b = 0, sum = 00
a = 0, b = 1, sum = 01
a = 1, b = 0, sum = 01
a = 1, b = 1, sum = 10
result bit is a xor b
carry bit is a and b
circuit with two inputs, a and b, and two outputs, sum and carry, is a half adder
what about carry in from the previous bit?

sum of three bits, a, b, and carry (c):
a b c sum
0 0 0 00
0 0 1 01
0 1 0 01
0 1 1 10
1 0 0 01
1 0 1 10
1 1 0 10
1 1 1 11
first (less significant) output is result
second (more significant) output is carry out
in-class exercise (5 minutes, alone): use two half adders and an OR gate to build this

carry out of less significant full adder can be connected to carry in of next full adder to give adder for any size words
time for carry propagation on addition of size n is proportional to n
solution ( carry save adder) with log(n) time:
- carry is generated when we have two "1" inputs (AND is high)
- carry is propagated when we have at least one "1" input (OR is high)
- these can be computed on a bit-wise basis
- carry-in for bit i is high if: generated by bit i-1, or propagated by bit i-1 and generated to the left of bit i-1

n-bit full adder
one of the inputs (traditionally, B), goes through an n-bit controlled inverter
the control line also goes into the carry-in of the adder, so that:
- when the control line is low, B is unchanged, and the output is A+B+0 (arithmetic addition), since the carry in is zero
- when the control line is high, B becomes (not(B)) , and the output is A+overline{B}+1 = A + B' = A - B
R-S latches (if time permits)