Today's Outline

Gates with more than 2 inputs

AND, OR, NAND, NOR gates can have multiple inputs
AND: output is high only if all inputs are high, low otherwise
NAND: output is low if all inputs are high, high otherwise
OR: output is low only if all inputs are low, high otherwise
NOR: output is high if all inputs are low, low otherwise
positive vs. negative logic: high and low do not have to be 1 and 0, could be 0 and 1

NOR gate:

AND gate:

A B OUT
0 0 0
0 1 0
1 0 0
1 1 1

If the inputs to the AND gate are inverted, the two truth tables are the same.

from the above example, the NOR of A and B is the same as the AND of the inverses of A and B:
(not(A+B)) = (not A) (not B)
This is true no matter how complicated A and B are.
the AND gate with the two inputs inverted is a bubbled AND gate
for 3 inputs: (not(A+B+C)) = (not(A)) (not(B)) (not(C))
for 4 inputs: (not(A+B+C+D)) = (not(A)) (not(B)) (not(C)) (not(D))
De Morgan's first law allows us to rearrange a circuit to look for:
- simpler equivalent
- better understanding

(not(AB)) = (not A) + (not B)
the OR gate with the two inputs inverted is a bubbled OR gate
for 3 inputs: (not(ABC)) = (not(A)) + (not(B)) + (not(C))
for 4 inputs: (not(ABCD)) = (not(A)) + (not(B)) + (not(C)) + (not(D))
in-class exercise: show that two four-input NANDs feeding into a two-input NAND are equivalent to two four-input ANDs feeding into a two-input OR

(A (not B)) + ((not A) B) = not (((not A) + B) (A + (not B)))
in-class exercise: convince your neighbor that the above equation is correct. Do this in two ways (neighbor A does the first, neighbor B the second):
1. by applying De Morgan's laws, and
2. by computing all possible values of the two logic functions

2-input exclusive OR has a 1 output if one, or the other, but not both, its inputs is zero
exclusive-NOR is the same as XOR, but the output is inverted
in-class exercise: design an implementation of XOR using two AND gates, two inverters, and an OR gate
what happens if we connect multiple XOR gates together? We get a 3-input, 4-input, or n-input XOR gate
in-class exercise: write the truth table for a 3-input XOR gate implemented by tying the output of a two-input XOR to a second XOR

the parity for a word is the least significant bit of the result of adding all the bits together
for example, the word 10010101010111 has parity bit 0, or even parity
the word 11010101010111 has parity bit 1, or odd parity
an n-input XOR gate produces the parity bit for an n-bit word
if we store the parity bit with the word, we can detect single-bit errors (even in the parity bit!)

also called a programmed inverter
a regular inverter always inverts
we want an inverter that will only invert when its control line is high
solution: use an (array of) XOR
when control is low, word passes through unchanged: Y = A
when control is high, word passes through inverted: Y = (not(A))
example: 4 bit controlled inverter
inverting is different from negation! For negation, you must add 1
in-class exercise: try adding a 4-bit number (first bit is 0, second bit is 1) and its inverse, then the same four-bit number and its inverse+1. Then repeat with an 8-bit number.

get checked off no later than Wednesday, September 17
use a voltmeter, power supply, NOR gates, LEDs
using only NOR gates, design, build, and show in operation:
- an inverter
- an AND gate
- an OR gate
using XOR gates, and LEDs (with resistors to limit the current and/or provide a voltage divider) and switches, design, build, and show in operation:
a controlled inverter for a 4-bit input