SAP-1, SAP-2

• SAP-1:
  • microprogram
  • controller implementation
• SAP-2:
  • architectural differences from SAP-1
  • bidirectional registers
  • instruction set
  • flags

SAP-1 Execution Cycle -- OUT

• in-class exercise
• work in groups of two
• 10 minutes
• draw a timing diagram: which signals are asserted on which cycle? (see Figure 10-5)

Microprogram

• controller must, on each clock cycle, produce 12 bits
• some of these bits are on-off (e.g. three-state output lines) and have a "default off" state
• some of these bits are A/B (e.g. the add-subtract line) and have a "default don't care"
• some bits are active high, some are active low

Controller Implementation

• how to generate microwords?
• if a bit is only on during one cycle, connect it to the corresponding ring counter bit
• if a bit is only on for an instruction, connect it to that instruction (as decoded by a 4-bit 1-of-16 decoder)
• if a bit is only on for an instruction and a cycle, connect it to the AND of the ring counter bit and the decoder output
• if a bit is on for multiple instruction and/or cycles, work out the truth table and use AND/OR or multiplexers to implement it
• alternative: use a ROM

Architectural Changes

• Jump Instructions: loadable PC
• 16-bit program counter
• 8-bit opcode, 42 instructions
• 2 input ports, 2 output ports
• 2K ROM, up to 62K RAM (16-bit addresses) with read and write
• memory data register (MDR) buffers reads and writes
• accumulator can write to bus
• tmp, B, and C registers
• 16 arithmetic and logic operations in ALU
• sign and zero flag

Bidirectional registers

• connect the inputs to the outputs
• load and enable never simultaneously active
• on load, outputs are 3-state, input is taken from the bus
• on enable, inputs are ignored, output goes to the bus
• 1/2 as many pins
• 1/2 as much bus capacitance

Instruction Set

• same fetch cycle (T₁, T₂, T₃) as SAP-1
• memory reference instructions: LDA, STA (3 bytes, lower byte before higher byte)
• immediate instructions: MVI reg, value (2 bytes)
• register instructions: MOV, ADD and SUB, INR and DCR, ANA, ORA, XRA, CMA (1 byte), ANI, ORI, XRI (2 bytes)
• jump and call instructions: JMP, JM, JZ, JNZ, CALL (3 bytes), RET (1 byte)
• CALL saves return address in memory FFFEH and FFFFH
• NOP, HLT, RAL, RAR (1 byte), IN, OUT (2 bytes)

In-Class Exercise 1

• hand-assemble the following program starting at address 2000H
• opcodes are: IN is DBH, "MOV B,A" is 47H, "DCR A" is 3DH, "MOV C,A" is 4FH, "ANA B" is A0H, "MOV A,C" is 79H, JNZ is 79H
• what does the program do?

START   IN 01H
LOOP    MOV B,A
        DCR A
        MOV C,A
        ANA B
        MOV A,C
        JNZ LOOP
DONE

Flags

• 2 flip flops, sign flag and zero flag
• set during arithmetic and logic operations to reflect final accumulator contents
• JM jumps only if the sign flag is set (minus result)
• JZ jumps only if the zero flag is set (zero result)
• JNZ jumps if the zero flag is clear (non-zero result)
• what is the value of the sign bit if the accumulator contents are zero?

In-Class Exercise

• work in groups of up to 3
• design a circuit to implement the flags
• inputs are: 8 bits from the accumulator, clock (use the positive-going edge), 1 L_F control line (active high)
• outputs are the flags: Z_F, S_F