Intel Architecture

• Special-Purpose Registers – Segment Registers – EFLAGS

– Control Registers

• Data Types – Unsigned Integers

– Signed Integers

– Pointers

• Operands – Immediate Operands – Register Operands – Memory Operands

Segment Registers

• Used in “Segmented Mode” addressing • 16-bit segment selectors

• CS: Code Segment

• SS: Stack Segment

• DS: Data Segment

• ES: “Extra” Segment (data)

• FS (data segment)

• GS (data segment)

CS and EIP Registers

• EIP: 32-bit Extended Instruction Pointer • EIP is offset into CS

• CS not loaded explicitly by application

Data Segment Registers

• DS, ES, FS, GS

• can be loaded by application programs • “general-purpose” segment registers • DI uses DS, EI uses ES

SS Register

• Points to stack segment • used by all stack operations

EFlags Register

• 32-bit register

• “Condition-Codes” (Status) and System Flags • Status Bits:

– Zero Flag (ZF)

– Sign Flag (SF)

– Carry Flag (CF) – unsigned overflow

– Auxiliary Carry Flag (AF)

– Overflow Flag (OF) – signed overflow

– Parity Flag (PF)

Branch Instructions

• JMP Jump always

• JE or JZ Jump on equal/zero

• JNE or JNZ Jump on not-equal/non-zero • JG or JNLE Jump on greater

• JGE or JNL Jump on greater or equal • JC Jump on carry set

• JO Jump on overflow

• JS Jump on sign set (negative)

• CALL call subroutine

• RET return from subroutine

Integers

• Signed or Unsigned

• 8 bits (byte)

• 16 bits (word)

• 32 bits (doubleword)

• Sign Bit is most significant

• least significant part of integer is in lowest address (little endian)

Integer Layout

Figures 5-1 and 5-2. Explain.

Pointers

• 32-bit (“near pointer”): – offset

– linear address

• 48 bit (“far pointer”): – 16-bit segment Identifier – 32-bit offset

Immediate Operands

• SPARC “literals”

• size allowed varies by instruction

• example: ADD EAX, 14, “14” is an immediate operand

• can only be the source operand in arithmetic operations

Register Operands

• 32-bit: EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP

• 16-bit: AX, BX, CX, DX, SI, DI, SP, BP

• 8-bit: AH, AL, BH, BL, CH, CL, DH, DL • Segment and Eflags registers

• 64-bit: pairs of registers (e.g EAX:EDX, EAX is the more significant)

Memory Operands

• Specified by 16-bit segment selector and 32-bit offset, or by 32-bit linear address

Segment Selectors

• Segment selector may be implicit:

Instructions CS instruction fetches
Stack  SS push/pop, references

using ESP or EBP

Data  DS Data references except

string destination

Data  ES String destination

• Segment selector may be explicit:

– MOV ES:[EBX], EAX; moves the value

from EAX to the segment pointed to by ES at offset given by EBX

– MOV DS, BX; moves the value from BX to the segment register DS.

– As part of far pointers

Segment Offsets

• effective address = EA

• Displacement is an 8-, 16-, or 32-bit constant • Base is a general-purpose register

• Index is a general-purpose register

• Scale is 2, 4, or 8

• Displacement, Base, and Index can be positive or negative.

• EA = Base + (Index ∗ Scale) + Displacement • Any one of these can be left out

• ESP cannot be index

• ESP or EBP as base imply SS as default segment, otherwise DS is default segment