Other Architectures: PDP-11

• context switch (finish)
• PDP-11 architecture
  • some history
  • CPU and memory organization
  • registers
  • addressing modes
  • 2-address instructions
  • 2-address register instructions
  • 1-address instructions
  • call and return
  • limitations

context switch

• we may decide to switch contexts, i.e. stop executing code for one process/thread and start executing code for another
• must:
  • save all thread-specific information on stack
  • save the stack pointer so we can later restart the thread
  • get stack pointer for the suspended thread
  • pop thread information from new stack
• in user mode: thread switch
• in supervisory mode: process switch (must change context register in MMU)
• assembly only (impossible in C)

context switch implementation

• save stack pointer
• save program counter (return address from call to this subroutine)
• save global floating point and flags registers
• save all the register windows: save until all register windows are on the stack
• do enough restore so window will underflow on next restore
• if switching processes, change MMU context (supervisory only)
• reload floating point, global registers, PC, SP
• restore to load topmost register window
• return to reloaded PC

PDP-11

• part of the Personal Data Processor family, which included the PDP-8
• 16-bit architecture
• Digital Equipment Corporation (DEC)
• introduced in the late 1970s
• relatively cheap, common in universities and research labs
• introduced when most computing was done in computing centers
• system on which Unix and C were first developed
• replaced in the 1980s by VAX and Sun

PDP-11 CPU

• user mode, supervisory mode, traps
• 16-bit basic instruction format
• CISC machine: to minimize number of instructions fetched, make instructions as powerful as possible
• no attempt to execute instructions in a single cycle
• no pipelining, no prefetching
• instructions include multiplication, division
• operands include byte, word (16 bits), optional floating point
• complex addressing modes

PDP-11 Memory

• 16-bit physical addresses -- no virtual memory, up to 64KB of physical memory
• little-endian: address points to low byte of word, next higher address addresses higher byte (SPARC is big-endian)
• registers mapped to memory?
• memory-mapped device registers (top 4KB of memory)
• alignment required for 2-byte quantities

PDP-11 Registers

• 8 16-bit GP registers
• 3 bits needed to identify register
• operand could also be in memory: 3 bits for addressing mode, 3 bits for register, 6 bits/operand
• one of the GP registers is the program counter, PC (patented by DEC?)
• one of the GP registers is the stack pointer, SP
• general increment/decrement access instructions ( *ptr++ in C) give us stack operations without special instructions

Addressing Modes

\setcounter{enumi}{-1}
1. register direct: next 3 bits indicate register with operand
2. register deferred: next 3 bits indicate register with pointer to operand
3. auto increment: *R is operand, and R is incremented
4. auto increment deferred: **R is operand, and R is incremented
5. auto decrement: R is decremented, then *R is operand
6. auto decrement deferred: R is decremented, then **R is operand
7. displacement: *(X+R) is operand
8. displacement deferred: **(X+R) is operand

Addressing Modes

• a single instruction may take several memory accesses, as on Intel
• relative addressing can be done by using the PC in one of the addressing modes
• examples:

        mov     (pc)+, r0
        .word   3756

        mov     *(pc)+, *(pc)+
        .word   3756
        .word   4024

PC Addressing Modes

• assembler uses special notation for PC-relative operands
• #n: operand follows instruction
• *#A: absolute address of operand follows instruction
• A: relative address of operand follows instruction
• *A: displacement is relative address of pointer to operand

2-address instructions

• mov/movb
• cmp/cmpb
• add
• sub
• bit/bitb
• bic/bicb
• bis/bisb

2-address register instructions

• destination is always register direct, so 3 more bits of instruction are available for encoding operation
• mul
• div
• ash
• ashc
• xor

1-address instructions

• all these (except swab) can be byte or word
• clr
• com
• inc
• dec
• neg
• tst
• swab
• ...

subroutine instructions

• jmp destination is given by addressing mode (operand)
• jsr destination is given by addressing mode (operand), current PC copied to specified register
• rts destination is given by register