Overview

• floating point
  • SPARC double floats
  • SPARC quad floats
  • Intel coprocessor
  • Intel formats
  • Intel operations
• processor state
• homework: exercise 11-3, due Fri Nov. 13th.

SPARC 64-bit Floating Point Representation

• 1 bit for the sign s (0 for positive, 1 for negative)
• 11 bits for the exponent e (2047 indicates NaN, Not a Number), in excess-1023 notation
• 52 bits for the fraction/significand/mantissa f
• n = (-1)^s * 2^{e-1023} * 1.f
• +oo is represented as 0x7ff0 0000 0000 0000
• +oo is represented as 0xfff0 0000 0000 0000
• class question: what ranges of numbers can be represented with double floats?

SPARC Double Float Instructions

SPARC Double Float Instructions

• all registers are double registers, only even-numbered registers may be specified
• all memory locations must be 8-byte aligned
• condition codes and branches are same as for single-precision
• absolute value and negation can be implemented with the single absolute value/negation instructions (which only affect the top bit) and fmovs

SPARC 128-bit Floating Point Representation

• 1 bit for the sign s (0 for positive, 1 for negative)
• 15 bits for the exponent e (2047 indicates NaN, Not a Number), in excess-1023 notation
• 122 bits for the fraction/significand/mantissa f
• n = (-1)^s * 2^{e-32767} * 1.f

Intel Math Co-processor

• Integer, BCD, and floating point representations
• floating point have sign bit, exponent (stored in excess notation), and mantissa:

  name	exponent	mantissa	bytes
  	bits	bits
  short	8	23	4
  long	11	52	8
  temporary	15	64	10

• 8 80-bit data registers, organized as a stack
• ST(0) is top of stack, ST(i) is i registers below the top (i must be constant)

Intel Floating Point Instructions

Intel Floating Point Instructions

• arguments that are not specified are taken from the stack
• many variants depending on whether stack is popped (...P instructions) or even popped twice (FCOMPP)
• tests set condition codes:
  • C0: less or unordered
  • C2: unordered
  • C3: equal or unordered
• FCOMI instructions set the integer condition codes (only from Pentium Pro upwards)

Processor execution modes

• user programs execute in user mode
• the OS executes in supervisory mode
• traps switch from user to supervisory mode
• rtt (return from trap) switches from supervisory to user mode
• certain operations (e.g. access all of memory) can only be done in supervisory mode
• this mechanism is sufficient for the OS to protect shared resources such as files, devices, network access

Processor state

• processor mode is one bit in the processor state register, PSR
• other state inaccessible from user mode includes:
  • program counters, PC and nPC
  • window invalid mask register, WIM
  • trap base register, TBR
  • Y register (used for multiplication)
  • floating point state register, FSR

Processor State Register

• S (supervisory) bit
• S bit is copied to PS (prior supervisory?) bit on a trap
• 4 bits hold the integer condition codes, ICC
• the EF bit is one if there is a floating-point co-processor
• 4 bits mark the processor interrupt level, PIL, which allows us to accept some interrupts while disabling others
• if the ET bit is set, traps are enabled
• 5 bits store the current window pointer, CWP

Window Invalid Mask register

• 32 bits
• WIM[CWP] = 1, all other bits are zero
• on save to stack, rotates right
• on restore from stack, rotates left
• SPARC allows between 2 and 32 register sets (architecture we have seen has 8)

Trap Base register

• 128 hardware traps (interrupts)
• 128 software traps
• interrupt table stores 4 instructions (16 bytes) for each interrupt/trap, for a total of 4K bytes
• usually at least 2 of those instructions are branch and delay slot
• trap base register stores pointer to the current trap in the interrupt table

Floating Point State register

• 2 bits of condition code
• 2 bits of rounding mode:
  • 0: round to nearest number (round 0.5 to 0, 1.5 to 2)
  • 1: round towards 0
  • 2: round towards +oo
  • 3: round towards -oo
• 5-bit exception field
• 5-bit exception mask field: exception causes trap only if corresponding mask bit is one
• in case of an exception, 3-bit FTT field indicates the trap