SPARC traps

• SPARC traps
• trap entry
• trap types
• trap exit
• interrupt priorities
• window traps

SPARC traps

• machine failure: reset
• memory failure: instruction/data/register access error, instruction/data access exception, unaligned access
• page faults: instruction/data MMU miss (virtual address not mapped to physical memory)
• window over/underflow
• privileged/illegal instruction
• fp/integer exceptions
• trap instruction
• interrupts

trap entry

1. clear ET (Enable Trap) bit (if already clear, reset machine). This disables all interrupts.
2. copy S bit to PS bit, and set S to 1 (supervisory)
3. decrement CWP (trap handler can use local registers)
4. store pc into %l0, npc into %l1, psr into %l2.
5. set trap type into tt field (bits 4-11) of TBR (trap base register)
6. load:
   • pc from [tbr]
   • npc from [tbr + 4]
7. start executing instructions again

trap types

• each interrupt and exception has its tt field
• the trap instruction ta has tt values 0x80...0xff
• low-order 7 bits of trap argument (+128) determine specific trap
• e.g. ta 0 gives a tt values of 0x80, for system calls

trap exit: re-execute instruction

	jmpl	%l0, %g0
	rett	%l1

• jmpl loads npc from %l0
• rett does:
  1. pc is set to npc from jmpl
  2. increment CWP
  3. load npc from %l1
  4. copy the PS bit to the S bit
  5. set ET to 1
• the sequence jmpl, rett is required
• thanks to jmpl, rett has no delay slot
• what if we want to skip over the instruction that executed the trap?

trap exit: execute next instruction

	jmpl	%l1, %g0
	rett	%l1 + 4

• jmpl loads npc from %l1
• rett does:
  1. pc is set to npc from jmpl
  2. increment CWP
  3. load npc with %l1 + 4
  4. copy the PS bit to the S bit
  5. set ET to 1
• why is the sequence jmpl, rett required?

interrupt priorities

• each interrupt and exception has a fixed priority
• before each instruction execution, highest priority interrupt is executed
• interruptlevel15 has priority 17, the highest interrupt priority
• interruptlevel1 has priority 31, the least
• PIL (processor interrupt level) field in PSR determines which interrupts can happen.
• interruptlevel15 cannot be disabled by PIL value
• traps and exceptions cannot be disabled
• assumption: disabled interrupt will persist until we lower the PIL

Notes:

register window traps

• what happens when we run out of register windows?
• Answer: trap to the kernel
• what can the kernel do?

register window overflow example

• 64 registers, 8 groups of 8
  1. in A
  2. local A
  3. out A -- in B
  4. local B
  5. out B -- in C
  6. local C
  7. out C -- in D
  8. local D
• when D starts execution, the WIM bit corresponding to the CWP is 1, marking the window as invalid
• when D executes save, we have a window overflow trap

window overflow trap: hardware response

• hardware decrements CWP to point to "invalid" window (with valid local registers)
• pc, npc, and psr saved into %l0...%l2
• user program cannot use local registers before CWP is decremented, CWP is decremented as part of trap, so local registers are available

window overflow trap: OS response

• decrement CWP again to point to the oldest register set
• copy registers to location pointed to by %sp of this register set
• copy in and local registers to location pointed to by %sp of this
• increment CWP twice to point to register set before save
• rotate WIM to indicate new valid window
• return from trap and re-execute save