My research focuses on algorithms for modern parallel systems. Most recently, I've been working on cache-efficient parallel algorithms for multicores and GPUs. Since efficient utilization of locality is essential for the performance on modern systems, I am interested in I/O-efficient algorithms, cache-oblivious algorithms and communication-efficient distributed algorithms (e.g. in the bulk-synchronous parallel (BSP) model and MapReduce) and limits of computation in these models (lower bounds). I am also interested in computational geometry and graph algorithms.

Publications

You can click on the title of the publication to view a PDF or click on next to the publication to see additional info, including abstract and links to the official publication on the publisher's website. You can also find my publications on Google Scholar and on DBLP. If you find any links missing or broken, please let me know.

As is customary in the algorithms research, most of my publications are in the alphabetical author order. The few publications, which appear in the venues where authorships is ordered by the contribution amount, are marked with (*).

Disclaimer: The papers are provided here for prompt dissemination of research results. For some of them the copyright is held by the respective publishers and should not be reproduced or republished elsewhere. The definitive versions are available from the official publishers' webpages by following the corresponding DOI link.

Conference Proceedings

  • N. Sitchinava, D. Strash. "Reconstructing Generalized Staircase Polygons with Uniform Step Length". In Proceedings of the 25th International Symposium on Graph Drawing (GD), 2017.

    Abstract: Visibility graph reconstruction, which asks us to construct a polygon that has a given visibility graph, is a fundamental problem with unknown complexity (although visibility graph recognition is known to be in PSPACE). We show that two classes of uniform step length polygons can be reconstructed efficiently by finding and removing rectangles formed between consecutive convex boundary vertices called tabs. In particular, we give an O(n2m)-time reconstruction algorithm for orthogonally convex polygons, where n and m are the number of vertices and edges in the visibility graph, respectively. We further show that reconstructing a monotone chain of staircases (a histogram) is fixed-parameter tractable, when parameterized on the number of tabs, and polynomially solvable in time O(n2m) under reasonable alignment restrictions.

    PDF DOI
  • R. Jacob, N. Sitchinava. "Lower bounds in the Asymmetric External Memory model". In Proceedings of the 29th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), pages 247-254, 2017.

    Abstract: Motivated by the asymmetric read and write costs of emerging non-volatile memory technologies, we study lower bounds for the problems of sorting, permuting and multiplying a sparse matrix by a dense vector in the asymmetric external memory model (AEM). Given an AEM with internal (symmetric) memory of size M, transfers between symmetric and asymmetric memory in blocks of size B and the ratio ω between write and read costs, we show Ω(min {N, (ωN/B) logω M/B (N/B)}) lower bound for the cost of permuting N input elements. This lower bound also applies to the problem of sorting N elements. This proves that the existing sorting algorithms in the AEM model are optimal to within a constant factor for reasonable ranges of parameters N, M, B, and ω. We also show a lower bound of Ω(min {H,(ωH/B) log ωM/B N/(max {δ, M}) for the cost of multiplying an N × N matrix with at most H=δN non-empty entries by a vector with N elements.

    PDF DOI
  • P. Afshani, M. deBerg, H. Casanova, B. Karsin, C. Lambrechts, N. Sitchinava, C. Tsirogiannis. "An efficient Algorithm for the 1D total visibility-index problem". In Proceedings of the 19th Meeting on Algorithm Engineering & Experiments (ALENEX), pages 218-231, 2017.

    Abstract: Let T be a terrain, and let P be a set of points (locations) on its surface. An important problem in Geographic Information Science (GIS) is computing the visibility index of a point p on P, that is, the number of points in P that are visible from p. The total visibility-index problem asks for computing the visibility index of every point in P. Most applications of this problem involve 2-dimensional terrains represented by a grid of n × n square cells, where each cell is associated with an elevation value, and P consists of the center-points of these cells. Current approaches for computing the total visibility-index on such a terrain take at least quadratic time with respect to the number of the terrain cells. While finding a subquadratic solution to this 2D total visibility-index problem is an open problem, surprisingly, no subquadratic solution has been proposed for the one-dimensional (1D) version of the problem; in the 1D problem, the terrain is an x-monotone polyline, and P is the set of the polyline vertices.

    We present an O(n log2 n) algorithm that solves the 1D total visibility-index problem in the RAM model. Our algorithm is based on a geometric dualization technique, which reduces the problem into a set of instances of the red-blue line segment intersection counting problem. We also present a parallel version of this algorithm, which requires O(log2 n) time and O(n log2 n) work in the CREW PRAM model. We implement a naive O(n2) approach and three variations of our algorithm: one employing an existing red-blue line segment intersection algorithm and two new approaches that perform the intersection counting by leveraging features specific to our problem. We present experimental results for both serial and parallel implementations on large synthetic and real-world datasets, using two distinct hardware platforms. Results show that all variants of our algorithm outperform the naive approach by several orders of magnitude on large datasets. Furthermore, we show that our new intersection counting implementations achieve more than 8 times speedup over the existing red-blue line segment intersection algorithm. Our parallel implementation is able to process a terrain of 224 vertices in under 1 minute using 16 cores, achieving more than 7 times speedup over serial execution.

    PDF DOI
  • * B. Karsin, H. Casanova, N. Sitchinava. "Efficient Batched Predecessor Search in Shared Memory on GPUs", in Proceedings of the IEEE International Conference on High Performance Computing (HiPC), pages 335-344, 2015.

    Abstract: Many-core Graphics Processing Units (GPUs) are being used for general-purpose computing. However, due to architectural features, for many problems it is challenging to design parallel algorithms that exploit the full compute power of GPUs. Among these features is the memory design. Although the issue of coalesced global memory access has been documented and studied extensively, another important architectural feature is the organization of shared memory into banks. The study of how bank conflicts impact algorithm performance has only recently begun to receive attention. In this work we study the predecessor search algorithm and the effects of bank conflicts on its execution time. Via complexity analysis we show that bank conflicts cause significant loss in parallelism for a naive algorithm. We then propose two improved algorithms: one that eliminates bank conflicts altogether but that uses a work inefficient linear search, and one that is work-optimal but that experiences a limited number of bank conflicts. We develop GPU implementations of these algorithms and present experimental results obtained on real-world hardware. These results validate our theoretical analysis of the naive algorithm and allow us to assess the performance of our algorithms in practice. Although both our improved algorithms outperform the naive algorithm, our main experimental finding is that our conflict-limited algorithm provides a larger performance gain.

    PDF DOI
  • P. Afshani, N. Sitchinava. "Sorting and permuting without bank conflicts", in Proceedings of the 23rd European Symposium on Algorithms (ESA), pages 13-24, 2015.

    Abstract:

    In this paper, we look at the complexity of designing algorithms without any bank conflicts in the shared memory of Graphical Processing Units (GPUs). Given input of size n, w processors and w memory banks, we study three fundamental problems: sorting, permuting and w-way partitioning (defined as sorting an input containing exactly n/w copies of every integer in [w]).

    We solve sorting in optimal O(n/w log n) time. When n ≥ w2, we solve the partitioning problem optimally in O(n/w) time. We also present a general solution for the partitioning problem which takes O(n/w log3 n/w w) time. Finally, we solve the permutation problem using a randomized algorithm in O(n/w log log log n/w n) time. Our results show evidence that when working with banked memory architectures, there is a separation between these problems and the permutation and partitioning problems are not as easy as simple parallel scanning.

    PDF ARXIV DOI
  • R. Jakob, T. Lieber, N. Sitchinava. "On the complexity of list ranking in the parallel external memory model", in Proceedings of the 39th International Symposium on Mathematical Foundations of Computer Science (MFCS), pages 384-395, 2014.

    Abstract: We study the problem of list ranking in the parallel external memory (PEM) model. We observe an interesting dual nature for the hardness of the problem due to limited information exchange among the processors about the structure of the list, on the one hand, and its close relationship to the problem of permuting data, which is known to be hard for the external memory models, on the other hand. By carefully defining the power of the computational model, we prove a permuting lower bound in the PEM model. Furthermore, we present a stronger Ω(log2 N) lower bound for a special variant of the problem and for a specific range of the model parameters, which takes us a step closer toward proving a non-trivial lower bound for the list ranking problem in the bulk-synchronous parallel (BSP) and MapReduce models. Finally, we also present an algorithm that is tight for a larger range of parameters of the model than in prior work.

    PDF DOI
  • P. Afshani, N. Sitchinava. "I/O-efficient range minima queries", in Proceedings of the 14th Scandinavian Symposium and Workshops on Algorithm Theory (SWAT), pages 1-12, 2014.

    Abstract: In this paper we study the offline (batched) range minima query (RMQ) problem in the external memory (EM) and cache-oblivious (CO) models. In the static RMQ problem, given an array A, a query rmqA(i,j) returns the smallest element in the range A[i,j]. If B is the size of the block and m is the number of blocks that fit in the internal memory in the EM and CO models, we show that Q range minima queries on an array of size N can be answered in O(N/B+Q/B logmQ/B)=O(scan(N)+sort(Q)) I/Os in the CO model and slightly better O(scan(N)+Q/B logmmin{Q/B,N/B}) I/Os in the EM model and linear space in both models. Our cache-oblivious result is new and our external memory result is an improvement of the previously known bound. We also show that the EM bound is tight by proving a matching lower bound. Our lower bound holds even if the queries are presorted in any predefined order. In the batched dynamic RMQ problem, the queries must be answered in the presence of the updates (insertions/deletions) to the array. We show that in the EM model we can solve this problem in O(sort(N)+sort(Q)logmN/B) I/Os, again improving the best previously known bound.

    PDF DOI
  • D. Ajwani, N. Sitchinava. "Empirical evaluation of the parallel distribution sweeping framework on multicore architectures", in Proceedings of the 21st European Symposium on Algorithms (ESA), pages 25-36, 2013.

    Abstract: In this paper, we perform an empirical evaluation of the Parallel External Memory (PEM) model in the context of geometric problems. In particular, we implement the parallel distribution sweeping framework of Ajwani, Sitchinava and Zeh to solve batched 1-dimensional stabbing max problem. While modern processors consist of sophisticated memory systems (multiple levels of caches, set associativity, TLB, prefetching), we empirically show that algorithms designed in simple models, that focus on minimizing the I/O transfers between shared memory and single level cache, can lead to efficient software on current multicore architectures. Our implementation exhibits significantly fewer accesses to slow DRAM and, therefore, outperforms traditional approaches based on plane sweep and two-way divide and conquer.

    PDF ARXIV DOI
  • M. Birn, V. Osipov, P. Sanders, C. Schulz, N. Sitchinava. "Efficient parallel and external matching", in Proceedings of the 19th International Conference Euro-Par 2013 Parallel Processing (Euro-Par), pages 659-670, 2013.

    Abstract: We study a simple parallel algorithm for computing matchings in a graph. A variant for unweighted graphs finds a maximal matching using linear expected work and O(log2 n) expected running time in the CREW PRAM model. Similar results also apply to External Memory, MapReduce and distributed memory models. In the maximum weight case the algorithm guarantees a 1/2-approximation. Although the parallel execution time is linear for worst case weights, an experimental evaluation indicates good scalabilty on distributed memory machines and on GPUs. Furthermore, the solution quality is very good in practice.

    PDF ARXIV DOI
  • L. Arge, J. Fischer, P. Sanders, N. Sitchinava. "On (dynamic) range minimum queries in external memory", in Proceedings of the 13th International Symposium on Algorithms and Data Structures (WADS), pages 37-48, 2013.

    Abstract: We study the one-dimensional range minimum query (RMQ) problem in the external memory model. We provide the first space-optimal solution to the batched static version of the problem. On an instance with N elements and Q queries, our solution takes Θ(sort(N + Q)) = Θ((N+Q)/B logM/B(N+Q)/B) I/O complexity and O(N + Q) space, where M is the size of the main memory and B is the block size. This is a factor of O(logM/BN) improvement in space complexity over the previous solutions. We also show that an instance of the batched dynamic RMQ problem with N updates and Q queries can be solved in O((N+Q)/B log2M/B(N+Q)/B) I/O complexity and O(N + Q) space.

    PDF DOI
  • N. Sitchinava, N. Zeh, "A parallel buffer tree", in Proceedings of the 24th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA) , pages 214-223, 2012.

    Abstract: We present the parallel buffer tree, a parallel external memory (PEM) data structure for batched search problems. This data structure is a non-trivial extension of Arge's sequential buffer tree to a private-cache multiprocessor environment and reduces the number of I/O operations by the number of available processor cores compared to its sequential counterpart, thereby taking full advantage of multicore parallelism.

    The parallel buffer tree is a search tree data structure that supports the batched parallel processing of a sequence of N insertions, deletions, membership queries, and range queries in the optimal O(sortP(N) + K/PB) parallel I/O complexity, where K is the size of the output reported in the process and sortp(N) is the parallel I/O complexity of sorting N elements using P processors.

    PDF DOI
  • M.T. Goodrich, N. Sitchinava, Q. Zhang, "Sorting, searching and simulation in the MapReduce framework", in Proceedings of the 22nd International Symposium on Algorithms and Computation (ISAAC), pages 374-383, 2011.

    Abstract: We study the MapReduce framework from an algorithmic standpoint, providing a generalization of the previous algorithmic models for MapReduce. We present optimal solutions for the fundamental problems of all-prefix-sums, sorting and multi-searching. Additionally, we design optimal simulations of the the well-established PRAM and BSP models in MapReduce, immediately resulting in optimal solutions to the problems of computing fixed-dimensional linear programming and 2-D and 3-D convex hulls.

    PDF ARXIV DOI
  • D. Ajwani, N. Sitchinava, N. Zeh, "I/O-optimal distribution sweeping on private-cache chip multiprocessors", in Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pages 1114-1123, 2011.

    Abstract: The parallel external memory (PEM) model has been used as a basis for the design and analysis of a wide range of algorithms for private-cache multi-core architectures. As a tool for developing geometric algorithms in this model, a parallel version of the I/O-efficient distribution sweeping framework was introduced recently, and a number of algorithms for problems on axis-aligned objects were obtained using this framework. The obtained algorithms were efficient but not optimal. In this paper, we improve the framework to obtain algorithms with the optimal I/O complexity of O(sortp(N) + K/PB) for a number of problems on axis aligned objects; P denotes the number of cores/processors, B denotes the number of elements that fit in a cache line, N and K denote the sizes of the input and output, respectively, and sortp(N) denotes the I/O complexity of sorting N items using P processors in the PEM model. To obtain the above improvement, we present a new one-dimensional batched range counting algorithm on a sorted list of ranges and points that achieves an I/O complexity of O((N + K)/PB), where K is the sum of the counts of all the ranges. The key to achieving efficient load balancing among the processors in this algorithm is a new method to count the output without enumerating it, which might be of independent interest.

    PDF DOI
  • D. Ajwani, N. Sitchinava, N. Zeh, "Geometric algorithms for private-cache chip multiprocessors", in Proceedings of the 18th European Symposium on Algorithms (ESA), pages 75-86, 2010.

    Abstract: We study techniques for obtaining efficient algorithms for geometric problems on private-cache chip multiprocessors. We show how to obtain optimal algorithms for interval stabbing counting, 1-D range counting, weighted 2-D dominance counting, and for computing 3-D maxima, 2-D lower envelopes, and 2-D convex hulls. These results are obtained by analyzing adaptations of either the PEM merge sort algorithm or PRAM algorithms. For the second group of problems--orthogonal line segment intersection reporting, batched range reporting, and related problems--more effort is required. What distinguishes these problems from the ones in the previous group is the variable output size, which requires I/O-efficient load balancing strategies based on the contribution of the individual input elements to the output size. To obtain nearly optimal algorithms for these problems, we introduce a parallel distribution sweeping technique inspired by its sequential counterpart.

    PDF DOI
  • L. Arge, M.T. Goodrich, N. Sitchinava, "Parallel external memory graph algorithms", in Proceedings of the 25th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pages 1-11, 2010.

    Abstract: In this paper, we study parallel I/O efficient graph algorithms in the Parallel External Memory (PEM) model, one o f the private-cache chip multiprocessor (CMP) models. We study the fundamental problem of list ranking which leads to efficient solutions to problems on trees, such as computing lowest common ancestors, tree contraction and expression tree evaluation. We also study the problems of computing the connected and biconnected components of a graph, minimum spanning tree of a connected graph and ear decomposition of a biconnected graph. All our solutions on a P-processor PEM model provide an optimal speedup of Θ(P) in parallel I/O complexity and parallel computation time, compared to the single-processor external memory counterparts.

    PDF DOI
  • L. Arge, M.T. Goodrich, M. Nelson, N. Sitchinava, "Fundamental parallel algorithms for private-cache chip multiprocessors", in Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), pages 197-206, 2008.

    Abstract: In this paper, we study parallel algorithms for private-cache chip multiprocessors (CMPs), focusing on methods for foundational problems that are scalable with the number of cores. By focusing on private-cache CMPs, we show that we can design efficient algorithms that need no additional assumptions about the way cores are interconnected, for we assume that all inter-processor communication occurs through the memory hierarchy. We study several fundamental problems, including prefix sums, selection, and sorting, which often form the building blocks of other parallel algorithms. Indeed, we present two sorting algorithms, a distribution sort and a mergesort. Our algorithms are asymptotically optimal in terms of parallel cache accesses and space complexity under reasonable assumptions about the relationships between the number of processors, the size of memory, and the size of cache blocks. In addition, we study sorting lower bounds in a computational model, which we call the parallel external-memory (PEM) model, that formalizes the essential properties of our algorithms for private-cache CMPs.

    PDF DOI
  • D. Eppstein, M.T. Goodrich, N. Sitchinava, "Guard placement for efficient point-in-polygon proofs", in Proceedings of the 23rd Annual ACM Symposium on Computational Geometry (SoCG), pages 27-36, 2007.

    Abstract: We consider the problem of placing a small number of angle guards inside a simple polygon P so asto provide efficient proofs that any given point is inside P. Each angle guard views an infinite wedge of the plane, and a point can prove membership in P if it is inside the wedges for a set of guards whose common intersection contains no points outside the polygon. This model leads to a broad class of new art gallery type problems, which we call "sculpture garden" problems and for which we provide upper and lower bounds. In particular, we show there is a polygon P such that a "natural" angle-guard vertex placement cannot fully distinguish between pointson the inside and outside of P (even if we place a guard at every vertex of P), which implies that Steiner-point guards are sometimes necessary. More generally, we show that, for any polygon P, there is a set of n+2(h-1) angle guards that solve the sculpture garden problem for P, where h is the number of holes in P (so a simple polygon can be defined with n-2 guards). In addition, we show that, for any orthogonal polygon P, the sculpture garden problem can besolved using n/2 angle guards. We also give an example of a class of simple (non-general-position) polygons that have sculpture garden solutions using O(√ n ) guards, and we show this bound is optimal to within a constant factor. Finally, while optimizing the number of guards solving a sculpture garden problem for a particular P is of unknown complexity, we show how to find in polynomial time a guard placement whose size is within a factor of 2 of the optimal number for any particular polygon.

    PDF DOI
  • * N. Sitchinava, S. Samaranayake, R. Kapur, E. Gizdarski, F. Neuveux, T.W. Williams, "Changing scan enable during shift", in Proceedings of the 22nd IEEE VLSI Test Symposium (VTS), pages 73-78, 2004.

    Abstract: This paper extends the reconfigurable shared scan-in architecture (RSSA) to provide additional ability to change values on the scan configuration signals (scan enable signals) during the scan operation on a per-shift basis. We show that the extra flexibility of reconfiguring the scan chains every shift cycle reduces the number of different configurations required by RSSA while keeping test coverage the same. In addition a simpler analysis can be used to construct the scan chains. This is the first paper of its kind that treats the scan enable signal as a test data signal during the scan operation of a test pattern. Results are presented on some ISCAS as well as industrial circuits.

    PDF DOI
  • * S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur, T.W. Williams, "A reconfigurable shared scan-in architecture", in Proceedings of the 21st IEEE VLSI Test Symposium (VTS), pages 9-14, 2003.

    Abstract: In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) architecture is defined. The composite architecture is created with analysis that relies on the compatibility relation of scan chains. Topological analysis and compatibility analysis are used to maximize gains in test data volume and test application time. The goal of the proposed synthesis procedure is to test all detectable faults in broadcast test mode using minimum scan-chain configurations. As a result, more aggressive sharing of scan inputs can be applied for test data volume and test application time reduction. The experimental results demonstrate the efficiency of the proposed architecture for real-industrial circuits.

    PDF DOI
  • Journal Articles

  • N. Sitchinava. "Computational geometry in the parallel external memory model". SIGSPATIAL Special 4(2): 18-23 (2012).

    Abstract: An overview of computational geometry results in the Parallel External Memory (PEM) model.

    PDF DOI
  • * S. Samaranayake, N. Sitchinava, R. Kapur, M. Amin, T.W. Williams, "Dynamic Scan: driving down the cost of test", IEEE Computer 35(10): 63-68 (2002).

    Abstract: Two factors primarily drive the soaring cost of semiconductor test: the number of test patterns applied to each chip and the time it takes to run each pattern. Typical semiconductor testing for each chip involves a set of 1,000 to 5,000 test patterns. These tests are applied through scan chains that operate at about 25 MHz. Depending on the size of the scan chains on the chip, a set of test patterns can take a few seconds to execute per chip. It's easy to see that even a small decrease in either the number of patterns or the time to execute them can quickly add up to big savings across millions of fabricated chips. This potential savings forms the basis for dynamic scan, a new approach to the well-established scan test methodology. The authors initial studies indicate that dynamic scan could easily reduce the time spent applying test patterns by 40 percent. A more theoretical analysis shows a potential savings of as much as 80 percent.

    PDF DOI
  • Refereed Workshops (without formally published proceedings)

  • N. Sitchinava, D. Strash. "Reconstructing a unit-length orthogonally convex polygon from its visibility graph". European Workshop on Computational Geometry (EuroCG), 2016.
  • P. Afshani, N. Sitchinava. "I/O-efficient range minima queries". 6th Workshop on Massive Data Algorithmics (MASSIVE), 2014.
  • N. Sitchinava, V. Weichert. "Provably-efficient GPU algorithms". 9th Scheduling for Large Scale Systems Workshop, 2014.
  • N. Sitchinava, V. Weichert. "Provably efficient GPU algorithms". 5th Workshop on Massive Data Algorithmics (MASSIVE), 2013.
  • L. Arge, J. Fischer, P. Sanders, N. Sitchinava. "On (dynamic) range minimum queries in external memory". 5th Workshop on Massive Data Algorithmics (MASSIVE), 2013.
  • D. Ajwani, N. Sitchinava, N. Zeh. "I/O-optimal distribution sweeping on private-cache chip multiprocessors". 3rd Workshop on Massive Data Algorithmics (MASSIVE), 2011.
  • D. Ajwani, N. Sitchinava, N. Zeh. "Geometric algorithms for private-cache chip multiprocessors". 2nd Workshop on Massive Data Algorithmics (MASSIVE), 2010.
  • L. Arge, M.T. Goodrich, N. Sitchinava. "Parallel external memory model". Workshop on Theory and Many-Cores (T&MC), 2009.
  • * N. Sitchinava, S. Samaranayake, R. Kapur, F. Neuveux, E. Gizdarski, T.W. Williams, "Dynamically reconfigurable shared scan-in architecture", IEEE International Test Synthesis Workshop (ITSW), 2004.
  • * N. Sitchinava, S. Samaranayake, R. Kapur, F. Neuveux, E. Gizdarski, T.W. Williams, D. Spielman, "A segment identification algorithms for a dynamic scan architecture", IEEE International Test Synthesis Workshop (ITSW), 2003.
  • * N. Sitchinava, S. Samaranayake, R. Kapur, M. Amin, T.W. Williams, "DFT - ATE solution to lower the cost of test", IEEE Workshop on Test Resource Partitioning, 2001.
  • Patents

    I am not a big fan of software patents because I believe that they hinder innovation. If you are interested, you can read more about arguments for and against software patents on this Wikipedia page. Regardless, in the past I worked at a company, which filed for patents and where I was listed as an inventor.

  • Dynamically reconfigurable shared scan-in test architecture. Inventors: R. Kapur, N. Sitchinava, S. Samaranayake, E. Gizdarski, F. Neuveux, S. Duggirala, T.W. Williams.

    US Patents: 7,900,105 7,836,368 7,836,367 7,774,663 7,743,299 7,596,733 7,418,640

  • Service

    Community Outreach

    I actively participate in career days in local middle and high schools to tell students about career opportunities in Computer Science.

    • Waipahu Intermediate School Career Day, Waipahu, HI, 2016
    • Waipahu Intermediate School Career Day, Waipahu, HI, 2015
    • Leilehua High School Career Day, Wahiawa, HI, 2014
    • Waipahu Intermediate School Career Day, Waipahu, HI, 2014