Memories, SAP-1
- Read-Only Memory
- diode ROM
- ROM, PROM, EPROM, EEPROM
- Random Access Memory
- static
- dynamic
- memory cycle: { (bar(CE)) }, { (bar(WE)) }
SAP-1
- architecture
- instruction set
Diode ROM
- rows connected to the output of a decoder: only the selected
row is high
- columns connected to the outputs of the RAM
- diodes from rows to columns raise the appropriate column (for a 1 bit),
or do not raise it (a 0 bit)
- addressing with a demultiplexer (demux) that raises the
correct row
ROM variants
- Read-only Memory (ROM): manufactured in bulk
- Programmable Read-only Memory (PROM): can be programmed once
- Erasable Programmable Read-only Memory (EPROM): a PROM that
can be programmed, then erased with UV light, then programmed again
- Electrically Erasable Programmable Read-only Memory (EEPROM): a
PROM that can be programmed, then erased with electrical signals, then
programmed again (slower than RAM, limited number of reprogrammings)
RAM variants
- core memory
- static RAM: a collection of D flip-flops
- volatile RAM: a capacitor controlled by a gate. The capacitor leaks
charge, so the memory must be refreshed every few milliseconds. The refreshing
is done by on-chip circuitry, but cannot proceed in parallel with memory
accesses
RAM read cycle
- raise (bar(WE))
- place address on address bus
- lower (bar(CE))
- after access time, read data on data bus
RAM write cycle
- lower (bar(WE))
- place address on address bus
- place data on data bus
- lower (bar(CE)) , hold it low for hold time
SAP-1
- Simple-As-Possible
- one output device (8 LEDs)
- 16 bytes of memory, read-only
- 5 instructions: 3 with 1 operand, 2 with implicit operands
- accumulator architecture: accumulator, out register,
and, architecturally invisible, B register, MAR, and IR
SAP-1 Architecture
- 8-bit "W" bus
- 4-bit program counter only counts up (starts execution at 0)
- 4-bit Memory Address Register (MAR)
- 16x8-bit memory
- 8-bit instruction register (IR)
- 6-cycle controller with 12-bit microinstruction word
- 8-bit accumulator
- 8-bit B register
- 8-bit adder-subtractor
- 8-bit output register
SAP-1 Instructions
| op | encoding | function |
|
LDA | 0000A3 ... A0 | acc = (A3 ... A0) |
|
ADD | 0001A3 ... A0 | acc = acc + (A3 ... A0) |
|
SUB | 0010A3 ... A0 | acc = acc - (A3 ... A0) |
|
OUT | 1110XXXX | out = acc |
|
HLT | 1111XXXX | suspend execution |
|
|
In-class exercise: what does this program output?
| adr | v | adr | v | adr | v | adr | v |
|
0H | 07 | 4H | F5 | 8H | 74 | CH | 38 |
|
1H | 16 | 5H | A1 | 9H | 65 | DH | 29 |
|
2H | 2F | 6H | 92 | AH | 56 | EH | 1A |
|
3H | E3 | 7H | 83 | BH | 47 | FH | 0B |
|
|