1. Introduction
Pan-STARRS (Panoramic Survey Telescope
and Rapid Response System) is an imaging facility being built by the
University of Hawaii's Institute for Astronomy. The system will
be composed of 4 optical systems, each containing a mirror and a very
high resolution camera. Each camera is made of orthogonal
transfer
charge coupled devices (OTCCD). Groups of these OTCCD's are
called orthogonal transfer arrays (OTA). The
OTCCD's are individually controlled to compensate for atmospheric phase
shifts in the observed sky. Control for these devices should be
automated. However, the logic levels are
~+12V, levels that are not compatible with normal programmable
logic devices (FPGA's). Therefore, a device that is able to
translate between the usual logic levels and
these higher logic levels (HVCMOS) has been designed. This HVCMOS
chip has high drive strength and is planned to be integrated with the
CCD's. The CCD's must be cooled in a chamber for performance
purposes. In the future, it is planned that the HVCMOS chip will
sit in the chamber with the CCD's.
My project will consist of designing a circuit board which can facilitate testing of the HVCMOS interface chips. The goal is to test the chip as it outputs a signal into a known load, using a USB connection to control the FPGA, which will control the HVCMOS chip. The FPGA will control the HVCMOS chip so that it can output a complex clock and timing sequence required by the CCD's. In addition to providing a way to test the output of the HVCMOS chip, my circuit board will have the capacity to connect with a daughter board containing a CCD (a miniature OTA, aka MOTA) to provide additional testing for the HVCMOS chip.
My project will consist of designing a circuit board which can facilitate testing of the HVCMOS interface chips. The goal is to test the chip as it outputs a signal into a known load, using a USB connection to control the FPGA, which will control the HVCMOS chip. The FPGA will control the HVCMOS chip so that it can output a complex clock and timing sequence required by the CCD's. In addition to providing a way to test the output of the HVCMOS chip, my circuit board will have the capacity to connect with a daughter board containing a CCD (a miniature OTA, aka MOTA) to provide additional testing for the HVCMOS chip.
2. Preliminary Block Diagram
